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CS1089 Vacuum Fluorescent Display Tube Driver
The VFD Driver is a microprocessor interface IC that drives a multiplexed VF (Vacuum Fluorescent) display tube. It consists of a 32-bit shift register, a 32-bit transparent data latch, a metal mask ROM, six 20 mA anode output drivers, twenty-three 2 mA anode output drivers, and three 50 mA grid drivers with output enables. Features Power On Reset Display Dimming Possible Three, 50 mA Grid Drivers Anodes: - 6 @ 20 mA - 23 @ 2 mA
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* * * *
DIP-40 WIDE BODY N SUFFIX CASE 711 40 1
PLCC-44 FN SUFFIX CASE 777
Chip Select
VIGN
12 V
Clock
Regulator 5V GND
ORDERING INFORMATION
Data Out SPI Functions
Device CS1089XN40
Package DIP-40 WIDE BODY PLCC-44 PLCC-44
Shipping 9 Units/Rail 23 Units/Rail 500 Tape & Reel
Anodes 1:29 0.1 F VCC P PORT PORT PORT GND PORT VBB FILAMENT VFD GRID1GRID2 GRID3 GND
CS1089XFN44 CS1089XFNR44
VBAT
CS1089 DOUT DIN GRID1 CLK GRID2 STB GRID3 GREN GND
DEVICE MARKING INFORMATION
See general marking information in the device marking section on page 7 of this data sheet.
Figure 1. Application Diagram
(c) Semiconductor Components Industries, LLC, 2001
1
August, 2001 - Rev. 9
Publication Order Number: CS1089/D
CS1089
MAXIMUM RATINGS*
Parameter Supply Voltage (VBB) Input Voltages (DIN, CLK, STB, GREN) Junction Temperature Range Storage Temperature Range ESD Susceptibility (Human Body Model) ESD Susceptibility (Machine Model) Package Thermal Resistance, DIP-40 Junction-to-Case, RJC Junction-to-Ambient, RJA Package Thermal Resistance, PLCC-44 Junction-to-Case, RJC Junction-to-Ambient, RJA Lead Temperature Soldering: 1. 10 second maximum. 2. 60 second maximum above 183C. *The maximum package power dissipation must be observed. Wave Solder (through hole styles only) Note 1 Reflow (SMD styles only) Note 2 Value -0.6 to +18 -0.6 to +6.0 -40 to +150 -55 to +150 2.0 200 20 45 16 55 260 Peak 230 Peak Unit V V C C kV V C/W C/W C/W C/W C
ELECTRICAL CHARACTERISTICS (8.0 V VBB 16.5 V, Gnd = 0 V, -40C TJ 105C; unless otherwise stated. Note 3.)
Parameter VBB Input VBB Input Voltage IBB0 Current Reset Mode DIN, CLK, STB Inputs VIL1, Input Low Voltage VIH, Input High Voltage IIL, Input Current GREN Input VIL, Input Low Voltage VIH, Input High Voltage IIH, Input Pull-down Current GRID1, GRID2, GRID3 Outputs IOL IOH VOL VOH AN24 - AN29 Outputs IOL IOH VOL VOH Sink Current Source Current IOUT = 400 A IOUT = -20 mA 400 20 - VBB - 0.5 - - - - - - 0.5 VBB A mA V V Sink Current Source Current IOUT = 1.0 mA IOUT = -50 mA, VBB = 12 V 1.0 50 - VBB - 0.75 - - - - - - 0.5 VBB mA mA V V VIN = 3.325 V - - - 3.3 - - - 30 1.6 - 60 V V A VIN = VIH - - - 3.3 - - - 7.5 1.6 - 20.0 V V A - No outputs active, VBB = 16.5 V All outputs forced low. 8.0 - - - 2.0 6.5 16.5 5.0 7.5 V mA V Test Conditions Min Typ Max Unit
3. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production.
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CS1089
ELECTRICAL CHARACTERISTICS (continued) (8.0 V VBB 16.5 V, Gnd = 0 V, -40C TJ 105C; unless otherwise stated.
Note 4.) Parameter AN1 - AN23 Outputs IOL IOH VOL VOG DOUT Output IOL IOH VOL VOH Sink Current Source Current IOUT = 1.0 mA IOUT = -1.0 mA 1.0 1.0 - 3.9 - - - - - - 0.5 5.1 mA mA V V Sink Current Source Current IOUT = 100 A IOUT = -2.0 mA 100 2.0 - VBB - 0.5 - - - - - - 0.5 VBB A mA V V Test Conditions Min Typ Max Unit
AC Characteristics: Input and Output Timing FC, CLK Frequency TCL, CLK Low Time TCH, CLK High Time TCR, CLK Rise Time TCF, CLK Fall Time TCD, CLK Low to DOUT Propagation Delay TSC, STB Low to CLK High Time TST, STB High Time TAN, STB High to Anode Output Propagation Delay TGL, Grid Turn On Propagation Delay TG0, Grid Turn Off Propagation Delay TGR, Grid Rise Time TGF, Grid Fall Time TAR, Anode Rise Time TAF, Anode Fall Time VBB = 12 V VBB = 12 V At rated load. Note 5. At rated load. Note 5. At rated load. Note 5. At rated load. Note 5. - - - - - - - - - 0 200 200 - - - 50 500 - - - 0.50 0.35 0.40 0.40 - - - - - - - - - - - - - - - 1.0 - - 100 100 200 - - 5.0 2.0 5.0 2.00 2.00 2.00 2.50 MHz ns ns ns ns ns ns ns s s s s s s s
4. Designed to meet these characteristics over the stated voltage and temperature ranges, though may not be 100% parametrically tested in production. 5. Grid and anode rise / fall times are measured from 10% and 90% points. Output currents are at the maximum rated currents for the respective stages.
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CS1089
PACKAGE LEAD DESCRIPTION
Package Lead Number 40L DIP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 44L PLCC 14 15 16 17 18 19 20 21 22 24 25 26 27 28 29 30 31 32 33 35 36 37 38 39 40 41 42 43 44 2 3 4 5 6 7 8 9 10 1, 11, 12, 23, 34 13 Lead Symbol (29 Anode Configuration) GRID1 GRID2 GRID3 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 GND AN17 AN18 AN19 AN20 AN21 AN22 AN23 AN24 AN25 AN26 AN27 AN28 AN29 DOUT DIN CLK STB GREN NC VBB 50 mA grid output. 50 mA grid output. 50 mA grid output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. Ground connection. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 2.0 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. 20 mA anode output. Shift register data output. Shift register data input. Shift register clock input. Transfer contents of shift registers to output stages. Grid outputs enable. No connection. Supply voltage input. Function
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CS1089
GRID1 GRID2 GRID3 AN1 AN2 AN3 AN23 AN24 AN25 AN26 AN27 AN28 AN29
VBB
VREG
POR GND
VREG
VREG GREN
VREG
METAL MASK ROM
STB
DQ VREG LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE
DQ LE VREG
DIN
DQ CLK VREG R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R DQ CLK R
DOUT
CLK
Output Drive Capability Grid Outputs: 5 mA AN24 - AN29: 20 mA AN1 - AN23: 2.0 mA
Figure 2. Block Diagram
OPERATION DESCRIPTION Upon the initial application of power, the power on reset function will cause all of the anode and grid driver outputs to be off and all shift register outputs to be set low. Data is fed into the shift register through the DIN pin at the rising edge of the CLK input. Thirty two bits of data are capable of being stored by the shift register. Once the desired pattern is stored in the shift register, it can be transferred to the latch by setting the STB input high. The output of each latch drives its corresponding output stage. A logic high input to the shift register/latch will cause the corresponding output to turn on. A logic low input to the shift register/latch will cause the corresponding output to turn off. Please note that if the STB is held high, the outputs of the latch reflect the outputs of the corresponding shift register bits and will change if data is shifted in. The three GRID outputs are gated by the GREN input. When GREN is low, the GRID outputs are forced low regardless of the state of the corresponding latch output. When GREN is high, the GRID outputs correspond to the state of their respective latch outputs. The anode outputs, AN1 to AN29 are always enabled. The DOUT pin is the output of the last stage of the shift register to allow serial cascading of this IC with other devices. Data from the last stage of the shift register is supplied to the DOUT pin delayed by 1/2 CLK cycle. Data on the DOUT output changes with the falling edges of the CLK to prevent logic race conditions between the CLK and the DIN of the next IC in the serial chain.
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CS1089
APPLICATION INFORMATION
Table 1. Bit Pattern, G = Grid, A = Anode.
Bit #
1 A1 17 A23
2 A2 18 A22
3 A3 19 A21
4 A4 20 A20
5 A5 21 A19
6 A6 22 A18
7 A7 23 A17
8 A8 24 G3
9 A16 25 A24
10 A15 26 A25
11 A14 27 A26
12 A13 28 A27
13 A12 29 A28
14 A11 30 A29
15 A10 31 G1
16 A9 32 G2
Pin Name
Bit #
Pin Name
1 CLKIN BIT 1
2
3
4
5
6
7
8
9
30
31
32
1
2
3
DIN
BIT 2
BIT 3
BIT 4
BIT 5
BIT 6
BIT 7
BIT 8
BIT 9
BIT 30 BIT 31 BIT 32 BIT 1
BIT 2
BIT 3
DOUT
PREV BIT 1
PREV BIT 2
PREV BIT 3
PREV BIT 4
PREV BIT 5
PREV BIT 6
PREV BIT 7
PREV BIT 8
PREV BIT 9
PREV BIT 30
PREV BIT 31
PREV BIT 32
PREV BIT 1
PREV BIT 2
PREV BIT 3
STB
ANODES
GREN
GRIDS *
* Selected grid goes high only if input bit pattern from shift register to grid is high.
Figure 3. Typical Operation
Unused grid and anode drivers should have their respective bits set to logic low in the data stream. Multiple grid or anode drivers may be connected together, but must be programmed to the same logic state for proper device operation. Maximum package power must be observed and care must be taken to maintian junction temperature below +150C. Care must be taken when interfacing this part to a microprocessor. The DOUT output VOH is specified at 3.9 V
to 5.1 V at an IOUT of -1.0 mA. Lower current loads will result in a higher output voltage. VOH = 5.2 V (typ) with no load. VOH = 5.7 V (max) with no load. Protection or workarounds for the device may be needed at the application level. No protection is needed when interfacing with other parts in this family (CS1087, CS1088, or CS1089).
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CS1089
MARKING DIAGRAMS PIN CONNECTIONS
40 CS1089 AWLYYWW 1
DIP-40 WIDE BODY N SUFFIX CASE 711
40
39 38 37 36 35 34 33 32 31 30 29 AN21 AN22 AN23 AN24 AN25 NC AN26 AN27 AN28 AN29 DOUT 40 41 42 43 44 1 2 3 4 5 6 28 27 26 25 24 23 22 21 20 19 18 7 8 9 10 11 12 13 14 15 16 17 DIN CLK STB GREN NC NC VBB GRID1 GRID2 GRID3 AN1 AN11 AN10 AN9 AN8 AN7 NC AN6 AN5 AN4 AN3 AN2
1 PLCC-44 FN SUFFIX CASE 777
CS1089 AWLYYWW
A WL, L YY, Y WW, W
= Assembly Location = Wafer Lot = Year = Work Week
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AN20 AN19 AN18 AN17 GND NC AN16 AN15 AN14 AN13 AN12
GRID1 GRID2 GRID3 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 AN16 GND
1
VBB NC GREN STB CLK DIN DOUT AN29 AN28 AN27 AN26 AN25 AN24 AN23 AN22 AN21 AN20 AN19 AN18 AN17
CS1089
PACKAGE DIMENSIONS
DIP-40 WIDE BODY N SUFFIX CASE 711-03 ISSUE C
40 21
B
1 20
NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25 (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 51.69 52.45 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0_ 15_ 0.51 1.02 INCHES MIN MAX 2.035 2.065 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0_ 15_ 0.020 0.040
A N
L C
J H G F D K
SEATING PLANE
M
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CS1089
PACKAGE DIMENSIONS
PLCC-44 FN SUFFIX CASE 777-02 ISSUE C
SCALE 1:1 -N- Y D B 0.007(0.180) U
M
T
L-M
M
S
N
S S
BRK
0.007(0.180)
T
L-M
N
S
Z -L- -M-
V
44 1
W
D
X VIEW D-D
G1 0.010 (0.25)
S
T
L-M
S
N
S
A R Z
0.007(0.180) 0.007(0.180)
M M
T T
L-M L-M
S S
N N
S S
H
0.007(0.180)
M
T
L-M
S
N
S
J C G G1 0.010 (0.25)
S
E 0.004 (0.10) -T- SEATING
PLANE
K1 K F 0.007(0.180) VIEW S
M
T
L-M
S
N
S
VIEW S
T
L-M
S
N
S
NOTES: 1. DATUMS -L-, -M-, AND -N- ARE DETERMINED WHERE TOP OF LEAD SHOULDER EXITS PLASTIC BODY AT MOLD PARTING LINE. 2. DIMENSION G1, TRUE POSITION TO BE MEASURED AT DATUM -T-, SEATING PLANE. 3. DIMENSIONS R AND U DO NOT INCLUDE MOLD FLASH. ALLOWABLE MOLD FLASH IS 0.010 (0.25) PER SIDE. 4. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 5. CONTROLLING DIMENSION: INCH. 6. THE PACKAGE TOP MAY BE SMALLER THAN THE PACKAGE BOTTOM BY UP TO 0.012 (0.300). DIMENSIONS R AND U ARE DETERMINED AT THE OUTERMOST EXTREMES OF THE PLASTIC BODY EXCLUSIVE OF MOLD FLASH, TIE BAR BURRS, GATE BURRS AND INTERLEAD FLASH, BUT INCLUDING ANY MISMATCH BETWEEN THE TOP AND BOTTOM OF THE PLASTIC BODY. 7. DIMENSION H DOES NOT INCLUDE DAMBAR PROTRUSION OR INTRUSION. THE DAMBAR PROTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE GREATER THAN 0.037 (0.940). THE DAMBAR INTRUSION(S) SHALL NOT CAUSE THE H DIMENSION TO BE SMALLER THAN 0.025 (0.635).
DIM A B C E F G H J K R U V W X Y Z G1 K1
INCHES MIN MAX 0.685 0.695 0.685 0.695 0.165 0.180 0.090 0.110 0.013 0.019 0.050 BSC 0.026 0.032 0.020 --0.025 --0.650 0.656 0.650 0.656 0.042 0.048 0.042 0.048 0.042 0.056 --0.020 2_ 10 _ 0.610 0.630 0.040 ---
MILLIMETERS MIN MAX 17.40 17.65 17.40 17.65 4.20 4.57 2.29 2.79 0.33 0.48 1.27 BSC 0.66 0.81 0.51 --0.64 --16.51 16.66 16.51 16.66 1.07 1.21 1.07 1.21 1.07 1.42 --0.50 2_ 10_ 15.50 16.00 1.02 ---
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Notes
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Notes
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CS1089
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer.
PUBLICATION ORDERING INFORMATION
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CS1089/D

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